Hy Ad001 User Manual
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Apr 11, 2017 - Charles Mingus-Mingus,Mingus,Mingus is hosted. Compilation album by Charles Mingus;. Download Charles Mingus Mingus Ah Um rar. Jan 23, 2018 - Charles Mingus – Mingus Ah Um (1959/1999) {SACD ISO + DSF DSF. Charles Mingus’ 1959 Columbia sessions were both a summation of his. Feb 7, 2012 - Charles Mingus - Mingus Mingus Mingus Mingus Mingus - 1963. Sinner Lady, Charles Mingus’ next sessions for Impulse found him looking back over a long and fruitful career. Rar-password: cazadam.blogspot. Feb 14, 2017 - Charles Mingus – Mingus Plays Piano (1963/1997) [HDTracks FLAC. Download charles mingus mingus mingus mingus rar. Jun 7, 2002 - Charles Mingus: The Very Best Of Charles Mingus jazz review by Mike Perciaccante, published on June 7, 2002. Find thousands reviews at All.
* Page 1: User Guide Integrator/IM-AD1 User Guide Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
*Page 2 Integrator/IM-AD1 User Guide Copyright © 2001-2003. All rights reserved. Release Information Date Oct 2001 Nov 2003 Proprietary Notice Words and logos marked with as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.
*Page 3 Conformance Notices This section contains conformance notices. Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c). CE Declaration of Conformity The system should be powered down when not in use. The Integrator generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
*Page 4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
* Page 5: Table Of Contents Hardware Reference ARM DUI 0163B About this book . viii Feedback . xi About the Integrator/IM-AD1 . 1-2 Interface module features and architecture . 1-4 Links and LEDs . 1-6 Care of modules . 1-7 Fitting the interface module . 2-2 Setting up the logic module .
*Page 6 Contents Chapter 4 Reference Design Example 4.10 4.11 4.12 4.13 Appendix A Signal Descriptions Appendix B Mechanical Specification Glossary CAN interface . 3-14 ADC and DAC interfaces . 3-18 About the design example . 4-2 Example APB register peripheral . 4-8 UART .
* Page 7: Preface Preface This preface introduces the Integrator/IM-AD1 interface module and its user documentation. It contains the following sections: • About this book on page viii • Feedback on page xi. ARM DUI 0163B Copyright © 2001-2003. All rights reserved.
* Page 8: About This Book Preface About this book This book provides user information for the ARM Integrator/IM-AD1 interface module. It describes the major features and how to use the interface module with an Integrator development platform. Intended audience This book is written for all developers who are using an Integrator/LM logic module to develop ARM-based devices.
*Page 9 Typographical conventions The following typographical conventions are used in this book: italic bold monospace monospace monospace italic monospace bold Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors. ARM periodically provides updates and corrections to its documentation.
*Page 10 The following publication provides information about Multi-ICE: • Multi-ICE User Guide (ARM DUI 0048). Third-party documents The following documents provide information about third-party components used on the Integrator/IM-AD1: • CC770 Stand Alone CAN Controller Target Specification Robert Bosch GmbH •.
* Page 11: Feedback Feedback ARM Limited welcomes feedback on both the Integrator/IM-AD1 and its documentation. Feedback on this document If you have any comments on this book, please send email to • the document title • the document number • the page number(s) to which your comments apply •.
*Page 12 Preface Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
*Page 13 Chapter 1 Introduction This chapter introduces the Integrator/IM-AD1. It contains the following sections: • About the Integrator/IM-AD1 on page 1-2 • Interface module features and architecture on page 1-4 • Links and LEDs on page 1-6 • Care of modules on page 1-7.
* Page 14: Chapter 1 Introduction The interface module is designed to be mounted on top of the logic module and provides connectivity for peripherals in the logic module FPGA. Figure 1-1 on page 1-3 shows the layout of the IM-AD1 and identifies the connectors. The IM-AD1 can be used to implement additional peripherals to aid software development, for example additional timers or a vector interrupt controller.
*Page 15 (J7) ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Introduction Stepper motor control (J19 and J20) SPI2 (J13) SPI1 (J11) D/A Outputs (J2) GPIO A (J17) GPIO B (J16) A/D Inputs (J1) (J3A and J3B)) Figure 1-1 Integrator/IM-AD1 layout.
* Page 16: Interface Module Features And Architecture Introduction Interface module features and architecture This section describes the main features of the interface module and its architecture. 1.2.1 Features The main features of the interface module are as follows: • two Bosch CC770 Controller Area Network (CAN) controllers •.
*Page 17 Chapter 3 Hardware Reference. ARM DUI 0163B Stepper motor interfaces CAN interfaces D to A converter A to D converter PWMs UART interface Figure 1-2 Integrator/IM-AD1 block diagram Copyright © 2001-2003. All rights reserved. Introduction.
* Page 18: Links And Leds Introduction Links and LEDs The interface module provides one link and one LED. These are the CONFIG link and CONFIG LED. Fitting the CONFIG link places all of the modules in the stack on which the interface module is mounted into CONFIG mode. This mode enables you to reprogram the FPGA image in the configuration flash on the logic module(s) using Multi-ICE (see the user guide for the logic module).
* Page 19: Care Of Modules Care of modules This section contains advice about how to prevent damage to your Integrator modules. To prevent damage to your Integrator system, observe the following precautions: • When removing a core or logic module from a motherboard, or when separating modules, take care not to damage the connectors.
*Page 20 Introduction Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
* Page 21: Chapter 2 Getting Started Chapter 2 Getting Started This chapter describes how to set up and start using the logic module. It contains the following sections: • Fitting the interface module on page 2-2 • Setting up the logic module on page 2-3 • Running the test software on page 2-4 ARM DUI 0163B Copyright ©.
* Page 22: Fitting The Interface Module Getting Started Fitting the interface module The interface module is installed at the top of a stack of up to four logic modules. However, it only provides interface connections for the logic module immediately beneath it. Figure 2-1 shows an example system comprising a core module and logic module attached to an Integrator/AP (see the Integrator/AP User Guide for more details).
* Page 23: Setting Up The Logic Module Switch 3 Open Switch 4 Open. The logic module will now be configured with the example design. If the IM-AD1 is not already fitted, install it on top of the logic module and the system is ready to use. ARM DUI 0163B Install_directoryIM-AD1configure program file.
* Page 24: Running The Test Software Getting Started Running the test software The supplied test program tests each of the interfaces on the IM-AD1. The example logic module configuration must be programmed into the logic module before the test program can be run. The test software requires various cables to be connected to the IM-AD1, details of.
*Page 25 Chapter 3 Hardware Reference This chapter describes the hardware interfaces and controllers on the interface module. This chapter contains the following sections: • Differences in signal routing between supported logic modules on page 3-2 • UART interface on page 3-3 •.
* Page 26: Differences In Signal Routing Between Supported Logic Modules Hardware Reference Differences in signal routing between supported logic modules The Integrator/LM-XCV600E+ and LM-EP20K600E+ logic module types route the signals from the interface module differently as follows: • LM-XCV600E+ is fitted with a Xilinx FPGA and routes the interface module ABANK[59:0] signals to bank 0 on the FPGA and the BBANK[53:0] signals to bank 1 on the FPGA.
* Page 27: Uart Interface UART interface The interface module provides one serial transceiver suitable for use with the PrimeCell UART (PL011) or other similar peripheral. Figure 3-1 shows the architecture of the UART interface. The signals associated with the UART interface are assigned to the EXPIM socket pins as shown in Table 3-1.
*Page 28 Hardware Reference The serial interface uses a 9-pin D-type male connector for which the pin numbering is shown in Figure 3-2. Table 3-2 shows the signal assignment for the connector. The serial interfaces signals operate at RS232 signal levels. Serial port functionality corresponds to the DTE configuration. Table 3-2 Serial connector signal assignment SER_DCD SER_RXD.
* Page 29: Spi This interface module provides two connectors for SPI ports. They are connected directly to the logic module FPGA and are used by the SSP PrimeCell (PL022) in the example configuration. Table 3-3 shows the assignment of the SPI signals to the logic module signals on the EXPIM connector.
* Page 30: Pwm Interface Hardware Reference PWM interface The interface module is fitted with a dual MOSFET switch. This provides two outputs that can be configured as Pulse Width Modulated (PWM) outputs or used as DC switches to switch external loads. The MOSFET can switch loads at up to 30V. Although the MOSFET is rated for 3A, because of the power dissipation of the package the maximum load current is 2.5A if only one PWM output is used or 1.75A if both outputs are used.
*Page 31 Table 3-5 shows the signal assignment. ARM DUI 0163B PWM1_+V PWM2_+V PWM1_SWITCH PWM2_SWITCH PWM1_FB PWM2_FB PWM_GND PWM_GND Copyright © 2001-2003. All rights reserved. Hardware Reference Table 3-5 PWM connector signals Description PWM supply voltage PWM switched load connection PWM feedback signal PWM ground.
* Page 32: Stepper Motor Interface Hardware Reference Stepper motor interface The IM-AD1 provides four stepper motor interfaces. Two of these, Step 1 and Step 2, are provided with on-board motor drivers for bipolar motors. The remaining two, Step 3 and Step 4, provide logic-level signals that are connected to two 10-pin headers. This enables you to connect to off-board motor drivers.
*Page 33 The current limit is set by the reference voltage and sense resistor according to the equation: peak Therefore, with a 0.1Ω sense resistor fitted: = 0.15 x 10 = 1.5A peak The reference voltage, and therefore the current limit, can be adjusted by altering the values of the divider resistors.
*Page 34 Hardware Reference Signal STEP2_PH1 STEP2_PH2 STEP2_PH3 STEP2_PH4 STEP3_ENA STEP3_ENB STEP3_PH1 STEP3_PH2 STEP3_PH3 STEP3_PH4 STEP4_ENA STEP4_ENB STEP4_PH1 STEP4_PH2 STEP4_PH3 STEP4_PH4 3.5.3 Stepper motor connectors Figure 3-6 shows the pin numbering of the stepper motor connectors. 3-10 Table 3-6 Stepper motor interface signals (continued) EXPB Description connector.
*Page 35 Table 3-7 shows the signal assignment. ARM DUI 0163B STEP1_VSS STEP2_VSS STEP1_O1 STEP2_O1 STEP1_O2 STEP2_O2 STEP1_O3 STEP2_O3 STEP1_O4 STEP2_O4 STEP_GND STEP_GND Copyright © 2001-2003. All rights reserved. Hardware Reference Table 3-7 Stepper motor connector signals Description Stepper motor supply Stepper motor drive output 1 Stepper motor drive output 2 Stepper motor drive output 3 Stepper motor drive output 4.
* Page 36: Gpio Hardware Reference GPIO The interface module provides two connectors for GPIO interfaces. Each connector provides 32 GPIO lines connected directly to the logic module FPGA. The connectors are shown in Figure 3-7. 3-12 +3V3 GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOA8.
*Page 37 Hardware Reference The example configuration includes two simple 32-bit GPIO controllers. GPIOA[31:0] connect to the EXPIM signals IM_ABANK[31:0] and GPIOB[31:0] connects to the EXPA signals B[31:0]. The B[31:0] signals can be monitored on the logic analyzer connector J7. ARM DUI 0163B Copyright ©.
* Page 38: Can Interface Hardware Reference CAN interface The IM-AD1 has two CAN interfaces provided by Bosch CC770 serial communications controllers. The network interfaces are provided by Philips TJA1050 transceivers, each capable of 1Mb/s data transfer. Figure 3-8 shows the architecture of the CAN interface. The CAN controllers are 5V devices and are supported by buffers at their interface with the 3.3V system buses.
*Page 39 All interface signals are routed to the logic module. The CAN controllers are supported by an AHB interface instantiated into the logic module code example supplied with the IM-AD1. The transmit and receive data signals, CANx_TXD and CANx_RXD, at the EXPIM connectors are not used for the normal operation of the interfaces.
*Page 40 Hardware Reference You connect the CAN interfaces through the 9-pin D-type plugs J3A (top) and J3B (bottom), with CAN1 connecting to J3A. Figure 3-9 shows the pin locations for this type of connector. 3-16 Table 3-8 CAN interface signal assignment (continued) EXPIM Signal connector.
*Page 41 Table 3-9 shows the signal assignment. ARM DUI 0163B Table 3-9 CAN connector signal assignments Copyright © 2001-2003. All rights reserved. Hardware Reference Not connected Not connected CAN1_L CAN2_L Not connected Not connected CAN1_H CAN2_H Not connected Not connected Not connected Not connected 3-17.
* Page 42: Adc And Dac Interfaces DAC_nWR All of the interface signals are routed to the FPGA on the logic module. The ADCs and DAC are supported by an AHB interface that is instantiated in the logic module code example supplied with the IM-AD1. 3-18 AD_D[15:0]_5V.
*Page 43 Table 3-10 shows the assignment of the ADC and DAC interface signals to the logic module signals on the EXPIM connector. Signal AD_D[15:0] AD_T/R AD_nOE ADC1_nCONV ADC1_nCS ADC1_nWR ADC1_nRD ADC2_nCONV ADC2_nCS ADC2_nWR ADC2_nRD ADC1_BUSY ADC2_BUSY DAC_nCLR DAC_nLDAC DAC_A0 DAC_nCS DAC_nWR ADC_CLK The ADCs are clocked from a 4MHz oscillator.
*Page 44 Hardware Reference The analog inputs to the ADCs are buffered by LMV324 operational amplifiers (op-amps). The op-amps are configured to give unity gain but the inputs have a resistive divider that divides the input voltage by 2. A 0-5V input signal range at the buffer inputs provides a 0-2.5V full range at the ADC input.
*Page 45 Figure 3-12 shows the pinout of the DAC interface connector (J2). ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Hardware Reference VOUTA VOUTB Figure 3-12 DAC connector pinout 3-21.
*Page 46 Hardware Reference 3-22 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
*Page 47 Chapter 4 Reference Design Example This chapter describes how to set up and start using the supplied example design. It contains the following sections: • About the design example on page 4-2 • Example APB register peripheral on page 4-8 •.
* Page 48: About The Design Example Reference Design Example About the design example This chapter describes the reference design example supplied with the interface module. The interface module is not fitted with any programmable devices because it is intended to provide interfaces for peripherals instantiated into a logic module FPGA. The interface module design example for the logic module is supplied in VHDL.
*Page 49 System Table 4-1 provides a summary description of the supplied VHDL files. A more detailed description of each VHDL block is included within the files in the form of comments. File Description This file is the top-level VHDL that instantiates all of the interface for the example. The VHDL for IMAD1fpga the PrimeCell interfaces are not supplied but are available from ARM as separate products.
*Page 50 Reference Design Example File Description This is the AHB multiplexor that connects the read data buses and the HRESP and HREADY AHBMux7S1M signals from all of the slaves to the AHB master. AHBZBTRAM An SSRAM controller block to support word, halfword, and byte operations to the SSRAM on the logic module.
*Page 51 0xF0000000 0xE0000000 0xD0000000 0xC0000000 The Integrator system implements a distributed address decoding scheme in which each core or logic module is responsible for decoding its own address space. It is important when implementing a logic module design, to ensure that t
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This electric air pump HY-AD001-A conforms to worldwide safety certification standards. With a strict quality control system, we manufacture fine products with nice designs and high-grade material for customers all over the world. Our products are patented worldwide; our patented structure allows for a longer usage life and largely increases. Dusty 1 yellowbella - Hurricane x hy ad001 - Solution manual fundamentals of vibrations leonard meirovitch - Manawa dharmasastra. Rechargeable Electric pump FD-607 Portable Rechargeable Electric Pump Hy-Ad001 User Manual - statslogoboss.netlify.app hurricane x hy ad001, how fail almost everything still, how to. View & download of more than 30 HYPE PDF user manuals, service manuals, operating guides. Toy, user manuals, operating guides & specifications.Arm enterprises, inc. interface module user guide. Hide thumbs 1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192
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AdvertisementHy Ad001 User Manual Transfer SwitchUser Guide Related Manuals for ARM IM-AD1 Summary of Contents for ARM IM-AD1Hy Ad001 User Manual Transmission
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Apr 11, 2017 - Charles Mingus-Mingus,Mingus,Mingus is hosted. Compilation album by Charles Mingus;. Download Charles Mingus Mingus Ah Um rar. Jan 23, 2018 - Charles Mingus – Mingus Ah Um (1959/1999) {SACD ISO + DSF DSF. Charles Mingus’ 1959 Columbia sessions were both a summation of his. Feb 7, 2012 - Charles Mingus - Mingus Mingus Mingus Mingus Mingus - 1963. Sinner Lady, Charles Mingus’ next sessions for Impulse found him looking back over a long and fruitful career. Rar-password: cazadam.blogspot. Feb 14, 2017 - Charles Mingus – Mingus Plays Piano (1963/1997) [HDTracks FLAC. Download charles mingus mingus mingus mingus rar. Jun 7, 2002 - Charles Mingus: The Very Best Of Charles Mingus jazz review by Mike Perciaccante, published on June 7, 2002. Find thousands reviews at All.
* Page 1: User Guide Integrator/IM-AD1 User Guide Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
*Page 2 Integrator/IM-AD1 User Guide Copyright © 2001-2003. All rights reserved. Release Information Date Oct 2001 Nov 2003 Proprietary Notice Words and logos marked with as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.
*Page 3 Conformance Notices This section contains conformance notices. Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c). CE Declaration of Conformity The system should be powered down when not in use. The Integrator generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
*Page 4 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
* Page 5: Table Of Contents Hardware Reference ARM DUI 0163B About this book . viii Feedback . xi About the Integrator/IM-AD1 . 1-2 Interface module features and architecture . 1-4 Links and LEDs . 1-6 Care of modules . 1-7 Fitting the interface module . 2-2 Setting up the logic module .
*Page 6 Contents Chapter 4 Reference Design Example 4.10 4.11 4.12 4.13 Appendix A Signal Descriptions Appendix B Mechanical Specification Glossary CAN interface . 3-14 ADC and DAC interfaces . 3-18 About the design example . 4-2 Example APB register peripheral . 4-8 UART .
* Page 7: Preface Preface This preface introduces the Integrator/IM-AD1 interface module and its user documentation. It contains the following sections: • About this book on page viii • Feedback on page xi. ARM DUI 0163B Copyright © 2001-2003. All rights reserved.
* Page 8: About This Book Preface About this book This book provides user information for the ARM Integrator/IM-AD1 interface module. It describes the major features and how to use the interface module with an Integrator development platform. Intended audience This book is written for all developers who are using an Integrator/LM logic module to develop ARM-based devices.
*Page 9 Typographical conventions The following typographical conventions are used in this book: italic bold monospace monospace monospace italic monospace bold Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors. ARM periodically provides updates and corrections to its documentation.
*Page 10 The following publication provides information about Multi-ICE: • Multi-ICE User Guide (ARM DUI 0048). Third-party documents The following documents provide information about third-party components used on the Integrator/IM-AD1: • CC770 Stand Alone CAN Controller Target Specification Robert Bosch GmbH •.
* Page 11: Feedback Feedback ARM Limited welcomes feedback on both the Integrator/IM-AD1 and its documentation. Feedback on this document If you have any comments on this book, please send email to • the document title • the document number • the page number(s) to which your comments apply •.
*Page 12 Preface Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
*Page 13 Chapter 1 Introduction This chapter introduces the Integrator/IM-AD1. It contains the following sections: • About the Integrator/IM-AD1 on page 1-2 • Interface module features and architecture on page 1-4 • Links and LEDs on page 1-6 • Care of modules on page 1-7.
* Page 14: Chapter 1 Introduction The interface module is designed to be mounted on top of the logic module and provides connectivity for peripherals in the logic module FPGA. Figure 1-1 on page 1-3 shows the layout of the IM-AD1 and identifies the connectors. The IM-AD1 can be used to implement additional peripherals to aid software development, for example additional timers or a vector interrupt controller.
*Page 15 (J7) ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Introduction Stepper motor control (J19 and J20) SPI2 (J13) SPI1 (J11) D/A Outputs (J2) GPIO A (J17) GPIO B (J16) A/D Inputs (J1) (J3A and J3B)) Figure 1-1 Integrator/IM-AD1 layout.
* Page 16: Interface Module Features And Architecture Introduction Interface module features and architecture This section describes the main features of the interface module and its architecture. 1.2.1 Features The main features of the interface module are as follows: • two Bosch CC770 Controller Area Network (CAN) controllers •.
*Page 17 Chapter 3 Hardware Reference. ARM DUI 0163B Stepper motor interfaces CAN interfaces D to A converter A to D converter PWMs UART interface Figure 1-2 Integrator/IM-AD1 block diagram Copyright © 2001-2003. All rights reserved. Introduction.
* Page 18: Links And Leds Introduction Links and LEDs The interface module provides one link and one LED. These are the CONFIG link and CONFIG LED. Fitting the CONFIG link places all of the modules in the stack on which the interface module is mounted into CONFIG mode. This mode enables you to reprogram the FPGA image in the configuration flash on the logic module(s) using Multi-ICE (see the user guide for the logic module).
* Page 19: Care Of Modules Care of modules This section contains advice about how to prevent damage to your Integrator modules. To prevent damage to your Integrator system, observe the following precautions: • When removing a core or logic module from a motherboard, or when separating modules, take care not to damage the connectors.
*Page 20 Introduction Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
* Page 21: Chapter 2 Getting Started Chapter 2 Getting Started This chapter describes how to set up and start using the logic module. It contains the following sections: • Fitting the interface module on page 2-2 • Setting up the logic module on page 2-3 • Running the test software on page 2-4 ARM DUI 0163B Copyright ©.
* Page 22: Fitting The Interface Module Getting Started Fitting the interface module The interface module is installed at the top of a stack of up to four logic modules. However, it only provides interface connections for the logic module immediately beneath it. Figure 2-1 shows an example system comprising a core module and logic module attached to an Integrator/AP (see the Integrator/AP User Guide for more details).
* Page 23: Setting Up The Logic Module Switch 3 Open Switch 4 Open. The logic module will now be configured with the example design. If the IM-AD1 is not already fitted, install it on top of the logic module and the system is ready to use. ARM DUI 0163B Install_directoryIM-AD1configure program file.
* Page 24: Running The Test Software Getting Started Running the test software The supplied test program tests each of the interfaces on the IM-AD1. The example logic module configuration must be programmed into the logic module before the test program can be run. The test software requires various cables to be connected to the IM-AD1, details of.
*Page 25 Chapter 3 Hardware Reference This chapter describes the hardware interfaces and controllers on the interface module. This chapter contains the following sections: • Differences in signal routing between supported logic modules on page 3-2 • UART interface on page 3-3 •.
* Page 26: Differences In Signal Routing Between Supported Logic Modules Hardware Reference Differences in signal routing between supported logic modules The Integrator/LM-XCV600E+ and LM-EP20K600E+ logic module types route the signals from the interface module differently as follows: • LM-XCV600E+ is fitted with a Xilinx FPGA and routes the interface module ABANK[59:0] signals to bank 0 on the FPGA and the BBANK[53:0] signals to bank 1 on the FPGA.
* Page 27: Uart Interface UART interface The interface module provides one serial transceiver suitable for use with the PrimeCell UART (PL011) or other similar peripheral. Figure 3-1 shows the architecture of the UART interface. The signals associated with the UART interface are assigned to the EXPIM socket pins as shown in Table 3-1.
*Page 28 Hardware Reference The serial interface uses a 9-pin D-type male connector for which the pin numbering is shown in Figure 3-2. Table 3-2 shows the signal assignment for the connector. The serial interfaces signals operate at RS232 signal levels. Serial port functionality corresponds to the DTE configuration. Table 3-2 Serial connector signal assignment SER_DCD SER_RXD.
* Page 29: Spi This interface module provides two connectors for SPI ports. They are connected directly to the logic module FPGA and are used by the SSP PrimeCell (PL022) in the example configuration. Table 3-3 shows the assignment of the SPI signals to the logic module signals on the EXPIM connector.
* Page 30: Pwm Interface Hardware Reference PWM interface The interface module is fitted with a dual MOSFET switch. This provides two outputs that can be configured as Pulse Width Modulated (PWM) outputs or used as DC switches to switch external loads. The MOSFET can switch loads at up to 30V. Although the MOSFET is rated for 3A, because of the power dissipation of the package the maximum load current is 2.5A if only one PWM output is used or 1.75A if both outputs are used.
*Page 31 Table 3-5 shows the signal assignment. ARM DUI 0163B PWM1_+V PWM2_+V PWM1_SWITCH PWM2_SWITCH PWM1_FB PWM2_FB PWM_GND PWM_GND Copyright © 2001-2003. All rights reserved. Hardware Reference Table 3-5 PWM connector signals Description PWM supply voltage PWM switched load connection PWM feedback signal PWM ground.
* Page 32: Stepper Motor Interface Hardware Reference Stepper motor interface The IM-AD1 provides four stepper motor interfaces. Two of these, Step 1 and Step 2, are provided with on-board motor drivers for bipolar motors. The remaining two, Step 3 and Step 4, provide logic-level signals that are connected to two 10-pin headers. This enables you to connect to off-board motor drivers.
*Page 33 The current limit is set by the reference voltage and sense resistor according to the equation: peak Therefore, with a 0.1Ω sense resistor fitted: = 0.15 x 10 = 1.5A peak The reference voltage, and therefore the current limit, can be adjusted by altering the values of the divider resistors.
*Page 34 Hardware Reference Signal STEP2_PH1 STEP2_PH2 STEP2_PH3 STEP2_PH4 STEP3_ENA STEP3_ENB STEP3_PH1 STEP3_PH2 STEP3_PH3 STEP3_PH4 STEP4_ENA STEP4_ENB STEP4_PH1 STEP4_PH2 STEP4_PH3 STEP4_PH4 3.5.3 Stepper motor connectors Figure 3-6 shows the pin numbering of the stepper motor connectors. 3-10 Table 3-6 Stepper motor interface signals (continued) EXPB Description connector.
*Page 35 Table 3-7 shows the signal assignment. ARM DUI 0163B STEP1_VSS STEP2_VSS STEP1_O1 STEP2_O1 STEP1_O2 STEP2_O2 STEP1_O3 STEP2_O3 STEP1_O4 STEP2_O4 STEP_GND STEP_GND Copyright © 2001-2003. All rights reserved. Hardware Reference Table 3-7 Stepper motor connector signals Description Stepper motor supply Stepper motor drive output 1 Stepper motor drive output 2 Stepper motor drive output 3 Stepper motor drive output 4.
* Page 36: Gpio Hardware Reference GPIO The interface module provides two connectors for GPIO interfaces. Each connector provides 32 GPIO lines connected directly to the logic module FPGA. The connectors are shown in Figure 3-7. 3-12 +3V3 GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOA8.
*Page 37 Hardware Reference The example configuration includes two simple 32-bit GPIO controllers. GPIOA[31:0] connect to the EXPIM signals IM_ABANK[31:0] and GPIOB[31:0] connects to the EXPA signals B[31:0]. The B[31:0] signals can be monitored on the logic analyzer connector J7. ARM DUI 0163B Copyright ©.
* Page 38: Can Interface Hardware Reference CAN interface The IM-AD1 has two CAN interfaces provided by Bosch CC770 serial communications controllers. The network interfaces are provided by Philips TJA1050 transceivers, each capable of 1Mb/s data transfer. Figure 3-8 shows the architecture of the CAN interface. The CAN controllers are 5V devices and are supported by buffers at their interface with the 3.3V system buses.
*Page 39 All interface signals are routed to the logic module. The CAN controllers are supported by an AHB interface instantiated into the logic module code example supplied with the IM-AD1. The transmit and receive data signals, CANx_TXD and CANx_RXD, at the EXPIM connectors are not used for the normal operation of the interfaces.
*Page 40 Hardware Reference You connect the CAN interfaces through the 9-pin D-type plugs J3A (top) and J3B (bottom), with CAN1 connecting to J3A. Figure 3-9 shows the pin locations for this type of connector. 3-16 Table 3-8 CAN interface signal assignment (continued) EXPIM Signal connector.
*Page 41 Table 3-9 shows the signal assignment. ARM DUI 0163B Table 3-9 CAN connector signal assignments Copyright © 2001-2003. All rights reserved. Hardware Reference Not connected Not connected CAN1_L CAN2_L Not connected Not connected CAN1_H CAN2_H Not connected Not connected Not connected Not connected 3-17.
* Page 42: Adc And Dac Interfaces DAC_nWR All of the interface signals are routed to the FPGA on the logic module. The ADCs and DAC are supported by an AHB interface that is instantiated in the logic module code example supplied with the IM-AD1. 3-18 AD_D[15:0]_5V.
*Page 43 Table 3-10 shows the assignment of the ADC and DAC interface signals to the logic module signals on the EXPIM connector. Signal AD_D[15:0] AD_T/R AD_nOE ADC1_nCONV ADC1_nCS ADC1_nWR ADC1_nRD ADC2_nCONV ADC2_nCS ADC2_nWR ADC2_nRD ADC1_BUSY ADC2_BUSY DAC_nCLR DAC_nLDAC DAC_A0 DAC_nCS DAC_nWR ADC_CLK The ADCs are clocked from a 4MHz oscillator.
*Page 44 Hardware Reference The analog inputs to the ADCs are buffered by LMV324 operational amplifiers (op-amps). The op-amps are configured to give unity gain but the inputs have a resistive divider that divides the input voltage by 2. A 0-5V input signal range at the buffer inputs provides a 0-2.5V full range at the ADC input.
*Page 45 Figure 3-12 shows the pinout of the DAC interface connector (J2). ARM DUI 0163B Copyright © 2001-2003. All rights reserved. Hardware Reference VOUTA VOUTB Figure 3-12 DAC connector pinout 3-21.
*Page 46 Hardware Reference 3-22 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B.
*Page 47 Chapter 4 Reference Design Example This chapter describes how to set up and start using the supplied example design. It contains the following sections: • About the design example on page 4-2 • Example APB register peripheral on page 4-8 •.
* Page 48: About The Design Example Reference Design Example About the design example This chapter describes the reference design example supplied with the interface module. The interface module is not fitted with any programmable devices because it is intended to provide interfaces for peripherals instantiated into a logic module FPGA. The interface module design example for the logic module is supplied in VHDL.
*Page 49 System Table 4-1 provides a summary description of the supplied VHDL files. A more detailed description of each VHDL block is included within the files in the form of comments. File Description This file is the top-level VHDL that instantiates all of the interface for the example. The VHDL for IMAD1fpga the PrimeCell interfaces are not supplied but are available from ARM as separate products.
*Page 50 Reference Design Example File Description This is the AHB multiplexor that connects the read data buses and the HRESP and HREADY AHBMux7S1M signals from all of the slaves to the AHB master. AHBZBTRAM An SSRAM controller block to support word, halfword, and byte operations to the SSRAM on the logic module.
*Page 51 0xF0000000 0xE0000000 0xD0000000 0xC0000000 The Integrator system implements a distributed address decoding scheme in which each core or logic module is responsible for decoding its own address space. It is important when implementing a logic module design, to ensure that t
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